The present invention relates generally to LDO (low dropout) voltage regulators, and more particularly to improvements in LDO voltage regulators which utilize an N-channel pass transistor and also provide both high PSRR (power supply rejection ratio, also referred to as power supply ripple rejection) and low VIN-to-VOUT voltage “headroom” at high frequencies. A conventional LDO, with either an NMOS or a PMOS pass device, is essentially a 3-terminal device having VIN, VOUT, and GND terminals. VIN not only delivers power to VOUT, but also is used as a supply voltage, sometimes referred to as a “supply rail”, for the LDO control circuit. In the case of N-channel pass transistor LDO, VIN can no longer be used as the supply rail for controlling the gate of an N-channel pass transistor of an LDO as VIN-to-VOUT becomes lower and lower (to be less than 0.7 volts), because N-channel MOS transistors need at least one gate-to-source (VGS) voltage, typically around 0.7 volts, to be turned on. That is why a separate voltage rail higher than VIN, either an external biasing rail VDD or an internally generated charge-pump voltage VCP, must be used to provide the gate drive for an N-channel MOS pass transistor. The penalties of using an external biasing voltage rail include limited use of N-channel pass transistor LDO's to systems where an extra high voltage rail is available and increased system complexity. The penalties for using an on-chip charge pump needed for N-channel LDO pass transistors include introducing switching noise and increasing the cost for integrated circuit die area. Nevertheless, the need to regulate from low input voltages makes it even more desirable to use N-channel MOS pass transistors in LDO voltage regulators because an N-channel MOS pass transistor can provide a lower dropout voltage (i.e., the VIN-to-VOUT voltage headroom) than a P-channel pass transistor due to the higher mobility of the charge carriers in N-channel transistors. In other words, the higher mobility charge carriers allow N-channel pass transistors to be substantially smaller and therefore less costly than P-channel pass transistors.
It has been very challenging to obtain high PSRR in voltage regulators having low dropout voltages because there is a trade-off between achieving high PSRR and reducing the size of the pass transistor. The PSRR for a linear regulator is defined as PSRR=vi(s)/vo(s), where vi(s) is the small AC excitation signal on VIN and vo(s) is the AC responsive signal on VOUT. For a given amount of dropout voltage or VIN-to-VOUT headroom, a larger MOS pass transistor operates closer to its saturation region and consequently provides better isolation of its regulated output voltage VOUT from ripple voltage components in its input voltage VIN. (By way of definition, the terms “ripple voltage” and “noise voltage” as used herein have generally the same meaning.)
Referring to Prior Art FIG. 1A, a typical low-dropout LDO voltage regulator 1A includes an error amplifier 2 and a large N-channel pass transistor MN1. The (+) input of error amplifier 2 is coupled to a reference voltage VREF, which is typically generated by a conventional band gap reference voltage circuit. A resistive voltage divider circuit including resistors R1 and R2 feeds a divided-down portion of the regulated output voltage VOUT back to the (−) input of error amplifier 2. The output of error amplifier 2 is coupled by conductor 3 to drive the gate of N-channel pass transistor MN1 acting as a source follower. Since the physical size of the N-channel pass transistor MN1 is relatively large, its gate-to-drain parasitic capacitance Cgd also is proportionately large, so the AC voltage component of the input voltage VIN can inject significant “displacement current” through the parasitic capacitance Cgd to the gate of pass transistor MN1, as indicated by arrow 9 in FIG. 1A. Since error amplifier 2 has finite output impedance ro, the injected displacement current generates a noisy ripple voltage related to the input ripple voltage on the gate of pass transistor MN1 (except for some phase shifts). Because of the source follower operation of pass transistor MN1, a “replica” of the noisy ripple voltage on the gate of pass transistor MN1 is passed onto VOUT conductor 6 as a corresponding ripple voltage component of VOUT. This degrades the PSRR of LDO voltage regulator 1.
FIG. 1B is a copy of a CMOS (complementary metal oxide semiconductor) LDO voltage regulator lB shown in the reference “A 25 mA 0.13 μm CMOS LDO Regulator with Power-Supply Rejection Better than −56 dB up to 10 MHz Using a Feedforward Ripple-Cancellation Technique”, by Mohamed El-Nozhi et al., ISSCC Digest of Technical Papers, pp. 330-331, February, 2009. The basic idea of this reference is to use ripple cancellation to improve the PSRR of a LDO voltage regulator that uses a P-channel pass transistor MP. In FIG. 1B, one can see that VIN drives the source of P-channel pass transistor MP and any ripple voltage in the VGS (gate-to-source-voltage) will be converted into ripple current to VOUT, causing PSRR degradation. By using a feed-forward amplifier 12 to duplicate the ripple noise component of VIN onto the gate of the P-channel pass transistor MP, the P-channel pass transistor MP does not “see” any ripple voltage component of VIN between its gate and source, so the PSRR is improved.
It can be seen that input ripple voltage cancellation for the LDO regulator of FIG. 1B can only be obtained within the bandwidths of the feed-forward amplifier 12 and summing amplifier 11, as the high frequency components in the input ripple voltage that are beyond the bandwidths of the two amplifiers can not be replicated to the gate of pass transistor MP. Moreover, in order to obtain optimal ripple voltage cancellation, pass device MP has to operate in its saturation region, as the cancellation is based on nullifying the ripple voltage superimposed on the gate-to-source voltage VGS of pass transistor MP so that no input ripple voltage can be converted to a ripple current flowing to the regulator output to cause PSRR degradation. However, as previously indicated, the pass transistor in an LDO voltage regulator usually operates in or near its linear region to improve power efficiency. If pass transistor MP in FIG. 1B is operating in its linear region, not only the output conductance of the pass transistor, gds, can be comparable to, or even larger than, its transconductance gm, but the output conductance also changes substantially with the load of the LDO regulator. The cancellation is not so effective because most of the noise coupled from VIN to VOUT passes through the output conductance gds of pass transistor MP. Also, it should be noted that although the cancellation technique of prior art FIG. 1B is effective for a P-channel pass transistor LDO, it is not applicable for an N-channel pass transistor LDO.
FIG. 1C is a copy of a CMOS LDO voltage regulator 50 shown in US Published Patent Application Pub. No. US2011/0193540 entitled “Enhancement of Power Supply Rejection for Operational Amplifiers and Voltage Regulators”, by Uday Dasgupta, filed Feb. 11, 2010 and published Aug. 11, 2011. This reference describes the implementation of PSRR improvement in an intermediate frequency range using feed-forward power supply ripple cancellation. A differential transistor pair 62 drives a load 64 to control the P-channel pass transistor MPD, in a conventional LDO. In addition, an amplifier 52 also drives load 64 to generate a feed-forward path for the power supply noise signal to cancel a power supply ripple voltage signal present on the gate of the pass transistor MPD. The cancellation is completed if the two signals are exactly equal and opposite. In this reference, the cancellation is optimized by digitally modifying the PSRR transfer function. Current signals resulting from the power supply ripple voltage are injected into a first stage to cancel first order terms in the PSRR transfer function, and a digital current gain adjustment circuit is used to optimize the PSRR, which occurs mainly within the bandwidth of the feedback loop. Similarly to the prior art shown in FIG. 1B, the effectiveness of the PSRR cancellation in Prior Art FIG. 1C is reduced when the operation of P-channel pass transistor MPD is near or in its linear operating region. Furthermore, the disclosed technique is not applicable to an N-channel pass transistor.
Thus, there is an unmet need for an LDO voltage regulator having an N-channel pass transistor, and also having substantially higher PSRR at higher frequencies than the closest prior art.
There also is an unmet need for an LDO voltage regulator having an N-channel pass transistor, and also having substantially higher PSRR at higher frequencies than the closest prior art irrespective of whether the pass transistor is operating near or in its linear region.